Coprocessor

Spec hygiene (canonical-spec.md rule 1). This document does not restate canonical values (current draw, clock, runtime delta). Those live in the Canonical Hardware Specification. Any value inline is a bug — fix it.

Role

The Pi Pico 2 (RP2350) is a realtime I/O coprocessor mounted on the internal sub-board alongside the Pi Zero 2 W. It owns two responsibilities the Pi can’t reliably handle from non-realtime Linux userspace:

YM2149 PSG synthesis with I2S out to the WM8960 codec (plus I²C to configure the codec, per ADR-0054). Audio underrun risk under heavy rendering load is eliminated by deterministic synthesis on dedicated silicon. See audio.md.
SSD1322 CIPHER-LINE OLED driver. Ticker cadence runs on the Pico’s own timer, immune to Linux scheduler jitter. See auxiliary-display.md.

The DMG cartridge bus role originally assigned to the Pico under ADR-0017 was removed by ADR-0019 — the cartridge interface moves to a USB-mass-storage SD card via a bridge IC on the internal hub, which the Pi reads directly. The Pico does not touch the cartridge. See cartridge-interface.md.

For the canonical module spec, see Canonical Hardware Specification — Coprocessor row.

Why RP2350 (not RP2040)

When ADR-0017 was authored the cart bus was the load-bearing reason for picking RP2350: 26 GPIOs on RP2040 couldn’t fit a 29-pin DMG bus without external multiplexing, while RP2350 fits cleanly. Post-ADR-0019 that argument is moot — there is no DMG bus.

The decision stands for the residual workload because:

PIO state-machine headroom — 12 SMs on RP2350 vs 8 on RP2040. After I2S audio output and OLED driver state machines land, RP2350 leaves comfortable room for future protocols (link cable for multi-deck linking, shoulder-button matrix, debug bus).
Cortex-M33 efficiency — more cycles/MHz than M0+; the YM2149 emulator + OLED ticker workload sits well inside the budget.
Secure-boot + supply — current-gen part with longer projected supply availability through the Q4 2027 ship target.

Reconsider only if power measurement at bring-up reveals RP2350 active draw materially above the ~25–55 mA midpoint.

Interfaces

Signal	Pico 2 GPIO	Connects to	Notes
UART0 RX	GPIO0	Pi GPIO15 (TX)	1 Mbps command link. See `software/api-reference/grammars/coprocessor-protocol.md`.
UART0 TX	GPIO1	Pi GPIO14 (RX)	Same link (full duplex).
BOOTSEL	(input)	Pi GPIO22	Pi-mediated flash flow — Pi pulses BOOTSEL low + RESET to enter UF2 USB-MSC mode (ADR-0017 §6). Pin TBD at bring-up if conflict.
RESET	(input)	Pi GPIO23	Same flow.
OLED bus to SSD1322	TBD at F2 firmware bring-up	CIPHER-LINE OLED	Canonical docs describe 4-wire SPI (MOSI, SCLK, CS, plus DC + RST control). GWP-619 bench verified an as-shipped 80xx/8080 harness on 2026-07-02; final product direction must be reconciled with `canonical-spec.md` and ADR-0015. See `auxiliary-display.md` and the `bench note` (deleted 2026-07-29; recover from git history).
I2S to WM8960 codec	TBD at F2 firmware bring-up	Stereo codec	BCLK, LRCLK, DOUT via PIO state machine. See `audio.md`.
I²C to WM8960 codec	TBD at bring-up (Pico expected)	Codec register config	SDA / SCL — WM8960 requires I²C register setup (unlike the strap-pin MAX98357A); master + address finalized at bring-up (per ADR-0054). See `audio.md`.
VBUS	(5 V in)	Main 5V rail	Common ground with the Pi. See `power.md`.
3V3 (OUT)	(3.3 V out)	SSD1322 module power	All OLED-related signals + power on a single ground domain.

GPIO finalisation (ADR-0017 §F9) closes during prototype bring-up.

Power

The Pico draws from the 5 V rail via VBUS, regulates internally, and drives the CIPHER-LINE OLED off its own 3.3 V output. Active draw and runtime delta are canonical values — see canonical-spec.md (Coprocessor + Battery rows) and power.md. Mid-band estimate is in canonical-spec.md; bring-up measurement at Stage 1c validates it.

Idle / dormant mode drops the Pico to <5 mA when audio is silent and the OLED is static — this is a tuning lever if the post-coprocessor runtime envelope misses target.

UART command protocol

Pi ↔ Pico is a 1 Mbps UART carrying length-prefixed binary frames with CRC-16/CCITT. Frame types are versioned; mismatch on the boot handshake fails to a clear error on Row 24 of the primary display.

Authoritative byte-level spec: software/api-reference/grammars/coprocessor-protocol.md. Cart-related frame types listed in that spec (CART_DETECT, CART_READ_BANK, CART_READ_SRAM, CART_WRITE_SRAM, CART_RESET) are obsolete under ADR-0019 and queued for cleanup; the audio (PSG_*) and OLED (OLED_*) frames remain authoritative.

Bootstrap

Pico boots from internal flash (<100 ms), opens UART, waits for HELLO.
Pi boots Linux from microSD (~5–10 s to userspace), nOSh sends HELLO. If no response within 1 s × 3 retries, Pi fails to a clear error.
VERSION_QUERY / VERSION_RESPONSE enforces firmware compatibility. Mismatch = hard fail.
Heartbeat ping every 5 s; 3 missed pings degrade the link and trigger Pico reset via GPIO23.

Resilience

Pico crash mid-mission: Pi watchdog resets the Pico (<100 ms reboot); audio glitches briefly; cart held inert until handshake recovers; mission state on Pi preserved.
Pi crash mid-mission: Pico continues current audio + OLED state for ~5 s, then idles to silence + holds last OLED frame. On Pi reboot, version handshake re-establishes; nOSh restores from Universal Deck State.

Firmware

Pico firmware lives at /lib/firmware/kn86-pico.uf2 on the Pi rootfs (per ADR-0020). The UF2 ships embedded inside the Pi system image; the Pi flashes the Pico automatically during boot when the version handshake detects mismatch — version coupling is enforced by construction (Pi rootfs + Pico UF2 ship as one .kn86fw artifact).

The Pico firmware source tree is kn86-pico/ (F2 deliverable per ADR-0017 — pico-sdk + cmake build, UART parser, PIO programs for I2S, YM2149 emulator port, OLED driver). Not yet implemented as of 2026-04-25; the desktop emulator routes nosh_psg_* and nosh_oled_* calls through an in-process coproc.c stub (landed GWP-250) that mirrors the eventual UART path.

Bring-up

Stage 1c in build-specification.md §4. Mount Pico, wire UART0 + BOOTSEL/RESET, wire peripheral pins (OLED bus, I2S + I²C to the WM8960 codec), flash firmware, verify handshake, joint power measurement under audio + OLED load.

GWP-619 proved the Pico board and OLED bus with a scratch UART-driven 8080 shell. That shell is a bench tool only: it does not implement the binary coprocessor protocol and should not be treated as the final kn86-pico firmware.

Stage 1c runs before Stage 1b (auxiliary display) and Stage 2 (audio) post-ADR-0017, even though the stages are numbered chronologically by ADR landing order. The Pico must be alive before the OLED and audio can be brought up against the Pico-owned OLED bus and I2S host.

Sourcing

BOM line 1b in sourcing-guide.md. Suppliers: Adafruit, Pimoroni, Raspberry Pi direct (same channels as the Pi Zero 2 W). Order 2 units; the Pico module is pin-compatible with the original Pico (RP2040) for prototype flexibility.

Production tooling will likely move from a Pico 2 module to a bare RP2350 chip on a custom sub-board (smaller footprint, lower BOM, no on-module USB we don’t use). Decision deferred to first production-tooling pass.